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DSD 2017 Dependability, Testing, and Fault Tolerance in Digital Systems

Call for Papers:
Dependability, Testing, and Fault Tolerance in Digital Systems (DTFT)

Download the call for papers in pdf format >>

Special Session Scope

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed HW/SW system engineering, covering the whole design trajectory from specification down to micro-architectures, digital circuits and VLSI implementations. It is a forum for researchers and engineers from academia and industry working on advanced investigations, developments and applications. It focuses on today and future challenges of advanced embedded, high-performance and cyber-physical applications; system and processor architectures for embedded and high-performance HW/SW systems; design methodology and design automation for all design levels of embedded, high-performance and cyber-physical systems; modern implementation technologies from full custom in nanometer technology nodes, through FPGAs, to MPSoC infrastructures.

Every designed system has to be tested several times during its life-time - during its design, production, and its in-field operation. The need for testing strictly depends on the actual use of the system, if the system can be repaired or not, and on the requirements for the system, e.g., if the system must be dependable, fault-tolerant, etc. The design must reflect these requirements. The special session on "Dependability, Testing, and Fault Tolerance in Digital Systems" (DTFT) addresses emerging issues, hot problems, new solution methods and their hardware and software implementations in all fields of digital and analog/mixed-signal system dependability and testing. It is especially focused on testing, dependability, and fault-tolerance of SoC based designs and modern embedded applications.

Papers on any of the following and related topics can be submitted to the special session:

  • Diagnosis & testing of embedded systems, SoC and NoC testing
  • Memory and CPU testing
  • Analog, mixed-signal and RF, IDDQ and current testing
  • Built-In Self-Test: off-line BIST and on-line BIST, test compression methods
  • Testability analysis, design for testability
  • Error detection and correction, on-line testing, design of checkers
  • Design of dependable (robust) circuits and systems, error mitigation techniques
  • Defect/fault tolerant architectures (SoCs, NoCs, embedded systems)
  • FPGA based fault tolerant systems, partial/full reconfiguration based methods
  • Fault injection techniques, fault simulation/emulation
  • Dependability modeling, dependability analysis and validation
  • Formal approaches in fault tolerant systems design
  • System diagnosis
  • Dependable design in practical applications

Submission Guidelines

Authors are encouraged to submit their manuscripts to Should an unexpected web access problem be encountered, please contact the Program Chair by email (dsd2017[at]

Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the IEEE format: single-spaced, double column, US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the manuscript, references included.

IEEE Conference Publishing Services (CPS) will publish accepted papers in the conference proceedings and the proceedings will be submitted to the IEEE Xplore Digital library and indexing services. Extended versions of selected best papers will be published in a special issue of the ISI indexed “Microprocessors and Microsystems: Embedded Hardware Design” Elsevier journal.

Special Session Chairs

P. Fišer (CTU in Prage, CZ)

Z. Kotásek (BUT, Brno, CZ)

Special Session Program Committee

S. Bernard, LIRMM, Montpellier (FR)

Ch. Bolchini, Politechnico di Milano (IT)

A. Bystrov, Newcastle University (UK)

G. Di Natale, LIRMM (FR)

G. Fey, Univ. of Bremen (DE)

P. Fišer, CTU in Prague (CZ)

T. Garbolino, Silesian TU, Gliwice (PL)

S. Kajihara, Kyushu Ins. of Tech. (JP)

M. Keim, Mentor Graphics, Wilsonville (US)

Z. Kotásek, BUT, Brno (CZ)

A. Krasniewski, WUT, Warsaw (PL)

H. Kubátová, CTU in Prague (CZ)

I. Levin, Tel Aviv University (IL)

H. Manhaeve, Q-Star Test (BE)

A. McEwan, University of Leicester (UK)

A. Miele, Politecnico di Milano (IT)

A. Orailoglu, UC, San Diego (US)

S. Racek, U. of West Bohemia (CZ)

J. Raik, Tallin U. of Technology (EE)

R. Růžička, BUT, Brno (CZ)

T. Sasao, Meiji University, Kawasaki (JP)

T. Sato, Fukuoka University (JP)

H. Shimada, Nagoya University (JP)

M. Sonza Reorda, Politecnico di Torino (IT)

V. Stopjaková, STU, Bratislava (SK)

R. Ubar, TTU, Tallinn (EE)

H. T. Vierhaus, Brandenburg U. Tech. (DE)

V.V. Veravalli, Vienna U. of Techn. (AT)

Y. Zorian, Virage Logic, CA (US)